In this paper, we propose an efficient architecture based on pre-computation for Viterbi decoders incorporating T-algorithm. Through optimization at both. A Fast ACSU Architecture for Viterbi Decoder Using T-Algorithm. Jinjin He, Huaping Liu, Senior Member, IEEE, and Zhongfeng Wang*, Senior Member, IEEE. High performance ACS for Viterbi decoder using pipeline T-Algorithm .. Z. Wang, A fast ACSU architecture for Viterbi decoder using T-Algorithm, in: Proc.
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A fast ACSU architecture for Viterbi decoder using T-algorithm – Semantic Scholar
How to cite item. Theoretically, when we continuously decompose Ps n-1Ps n-2 ,……, the precomputation scheme can be extended to Q steps. Ganesh KumarA. Through optimization at algorithm level greatly shortens the long critical path introduced by the T-algorithm.
Later in the next section we will report ASIC implementation results that have not been obtained earlier. Hence Popt n can be calculated directly from Ps n-q in q cycles. Also, any kinds of low-power scheme would introduce extra hardware like the purge unit shown in Fig. The results are shown in Table IV. In other words, the states can be grouped into m clusters, where all the clusters have the same number of states and all the states in the same cluster will be extended by the same Bs.
A fast ACSU architecture for Viterbi decoder using T-algorithm
Since the performance is the same as that of the conventional T-algorithm. So, the computational over head and decoding latency due to predecoding and re encoding of the TCM signal become.
Typically a TCM system employs a high rate convolutional code, which leads to high complexity of viterbi decoder for the TCM decoder, when the constraint length of Convolutional code is also normal. The operation of searching for the best path metrics in the add-compare-select loop in T-algorithm significantly limits the clock speed.
Low power Viterbi decoder for Trellis coded Modulation using T-algorithm
Architectuure, Bs are fed into the ACSU that recursively compute the path metrics Ps and outputs decision fof for each possible state transition. The 64 states and path metrics are labeled from 0 to References Publications referenced by this paper. It is worth to mention that the conventional T -algorithm VD takes slightly more hardware than the proposed architecture, which is counterintuitive.
It is well known that viterbi decoder is dominant module for finding the overall power consumption for the TCM decoders. General solutions for low power viterbi decoder design will be studied in our implementation work.
Low power Viterbi decoder for Trellis coded
Furthermore, the even states all extend to states with higher indices the MSB in Fig. At the receiver, a soft input VD should be employed to guarantee a good coding gain. Article Tools Print this article. Faat 1 0 ………………………. In , through a design example that, q -step pre- computation can be pipelined into q stages, where the logic delay of each stage is continuously reduced as q increases. In his section, we further address the SMU design issue.
Again, to simplify the evaluation, we consider, a code with a constraint length k and q precomputation steps. Email the author Login required.
The functional diagram of the 1-step pre-computation scheme is fot in Fig. In this paper we propose an architecture for viterbi decoder with T-algorithm which can effectively reduce the power consumption with a negligible decrease in speed.
We have also analyzed the precomputation algorithm, where the optimal precomputation steps are calculated and discussed.
Computational overhead compared with conventional T-algorithm is an important factor that should be carefully evaluated.
For VD in-corporated with T- algorithm, no state is guaranteed to be active at all clock cycles. This paper has 27 citations.
IC design of an adaptive Viterbi decoder. This information allows us to obtain the 2-step pre-computation data path.
Modern digital communication systems usually employ convolutional codes with large constraint length for good decoding performance, which leads to large complexity and power consumption in Viterbi decoders.